The AL100 PC to TV scan converter chip accepts graphic data from PC and Macintosh graphics controllers and converts them into broadcast-quality NTSC or PAL TV signals. In addition to analog RGB data, 24-bit digital RGB data can be input to maintain the best video quality and avoid noise problems. An integrated high-quality anti-flicker filter (SmartFilter (tm)) removes the unpleasant flicker caused by the interlaced display of high contrast graphics while maintaining the original clarity and sharpness of informative data such as natural pictures and text. The chip is fully programmable with I^ (2)C interface. In case I^ (2)C programming is not available, each single control register can also be programmed through VGA sync signals at a slower bit rate. The on-screen-menu combined with the software programmability serve as a friendly user interface for selecting video functions. With 512K bytes of memory, plug-and-play is achieved by automatically detecting the scan rate and resolution of the incoming graphic signals without the use of software. Each single pixel of graphic data up to 800 x 600 is processed and stored by using a complex and proprietary buffer management system, no compromise is made at all with video quality by using either compression or sub-sampling algorithms. The major functions of the AL100 can be accessed using four push buttons combined with the on-screen-menu feature, this eliminates the cost of a micro-controller and complex control panel. The superior quality scaling algorithm, which reduces the jagged-edge artifacts from line dropping, can smoothly fit graphics of 640 x 480 (up to 85 Hz) and 800 x 600 (up to 72 Hz) resolutions into the visible region of the NTSC or PAL screen. Additional features include four levels of sharpness control using 5-line filter, zoom control and picture freeze. The AL110 is a highly integrated mix-signal chip, packaged in 24mm x 24mm x1.4mm 160-pin TQFP (thin quad flat package). Power-down is achieved by using either hardware or software control. The AL110 is a highly integrated mix-signal chip, packaged in 20mm x 14mm x 14mm 128-pin LQFP (thin quad flat package). Power-down is achieved by using either hardware or software control. The enhanced features and superior quality make the AL100 very suitable for PC video to TV conversion in VGA add-on cards, Internet set-top boxes, or network and laptop PCs. Either analog RGB or digital RGB data can be input to the chip. The analog RGB data is digitized by three 8-bitvideo A/D's and is converted into 24-bit digit RGB data. For graphic controllers with standard or proprietary digital RGB output such as a high-color feature connector, VAFC, or flat panel interface, the optional 24-bit digital RGB interface provides a solution for optional video quality. There is no resolution drop during the A/D or D/A conversion processes or problem introduced in the analog video path or clock recovery circuits, which normally cause headaches for system manufactures. The 24-digital RGB is passed to the digital processing unit of the chip. This DSP unit dose the processing and scan conversion operations such as flicker filtering, YUV filtering, scaling and color space conversion data is sent to the digital TV encoder video data is sent to the digital TV encoder for converting into broadcast quality composite and S-video signals, which are in turn converted by three 9-bit D/A converters into analog outputs. The I^ (2)C interface provides full software programmability. Another option is to control the chip by programming the duty cycle of VGA sync signals at a slower bit-rate. The aforementioned hardware and software programmability also applies for the power-down feature. Alternatively only four push buttons are required to control the major functions such as sharpness, pan, zoom, brightness, color bar output and position centering.
Specifications:
Features:
- Applications:
- Multimedia
- TV output for laptop, network, entertainment PC
- Net browser/set-top box
- Internet TV
- VGA add-on card with TV output
- Convert non-interlaced VGA or Macintosh video into interlaced TV format (NTSC/PAL)
- High integrated design with built-in NTSC/PAL encoder, ADC, DAC, memory
- Broadcast TV quality
- High clarity 5-line anti-flicker filter
- 8 levels of sharpness control
- Plug and play with no need for software or micro-controller
- Automatically supports scan rate from 50 Hz up to 85 Hz
- Vertical and horizontal overscan / underscan control
- Zoom and freeze controls
- Four-touch-button interface with on-screen-menu (on TV) to control all key functions
- Horizontal and vertical panning and position centering control
- Optional digital 24-bit RGB/VAFC interface for best quality
- Power down feature controlled by software or hardware
- Full programmability via I^2 interface and/or VGA sync
- Brightness control
- Built-in color bar
- Simultaneous display on PC and TV monitors
- Thin, small TQFP package for PCMCIA or notebook applications
- Full resolution digital signal processing and buffer-no compression or sub-sampling
- 0.5 Mbytes of memory needed for either NTSC or PAL
Others:
| Symbol | Type | Pin | Description |
| /PWRDN | In (CMOSd) | 148 | Power down enable (active low) |
| /RESET | In (CMOSd) | 149 | Reset (active low) |
| AB | In (0.7V) | 129 | Analog blue |
| AC | Out (1 V p-p) | 37 | Analog chroma output |
| ACMP | out (1V p-p) | 41 | Analog composite output |
| Aden | In (CMOSd) | 7 | Use internal ADC; 0, use external ADC; 1, use internal ADC |
| AG | In (0.7V) | 132 | Analog green |
| AR | In (0.7V) | 137 | Analog red |
| AY | Out (1V p-p) | 39 | Analog luma output |
| Blue<7:0> | In (CMOSd) | 119-122, 124-127 | Graphic blue input data |
| CHROMA<7:0> | In (CMOSd) | 25-28, 30-33 | Digital chroma output |
| COMP | In (0.1uF) | 43 | Compensation Pin, 0.1uF pull-up |
| DEC | In (CMOSsd) | 4 | Decrement button |
| GCLK | In (CMOS) | 143 | Graphic pixel clock |
| GHSDIV | Out (CMOS) | 146 | Graphic pixel clock divide by M signal for external PLL circuits |
| GHSOUT | Out (TTL) | 145 | Graphic hsync output buffered from external VGA HSYNC |
| GHSQYNC | In (CMIOSd) | 140 | Graphic HSYNC |
| GREEN<7:0> | In (CMOSd) | 109-112, 114-117 | Graphic green input data |
| GVSOUT | Out (TTL) | 147 | Graphic vsync output buffered from external VGA VSYNC |
| GVSYNC | In (CMOSd) | 141 | Graphic VSYNC |
| I2C | In (CMOSd) | 12 | I2C bus connected; 0-enable VGA sync programming; 1-enable I2C programming |
| I2CADDR | In (CMOSd) | 11 | I2C sub address; 0-write address=88, read adress=89; 1-write address=8C, read address=8D |
| INC | In (CMOSsd) | 3 | Increment button |
| INTYPE<1:0> | In (CMOSd) | 156, 157 | Graphic input type; 00-24-bit RGB 01-reserved; 10-feature connector; 11-VAFC |
| LUMA<7:0> | OUT (CMOS) | 15-18, 20-23 | Digital luma/composite output |
| MD<15:0> | 47-50, 52-55, 80-83, 85-88 | Memory data to input of external field memory | |
| MEMCONF<1:0> | In (CMOSd) | 75, 76 | External memory configuration; 00-no external memory, 01-use field memory; 11-reserved |
| MEMTYPE | In (CMOSd) | 72 | Memory type; 0-reserved; 1-NEC D42280 |
| MENU | In (CMOSd) | 6 | Menu button |
| MQ<15:0> | In (CMOSd) | 57-60, 62-65, 90-93, 95-98 | memory data from output of external field memory |
| MRCLK | Out (CMOS) | 68 | Memory read clock |
| MREN | Out (CMOS) | 66 | Memory read enable |
| MRRST | Out (CMOS) | 69 | Memory read reset |
| MWCLK | Out (CMOS) | 73 | Memory write clock |
| MWENH | Out (CMOS) | 77 | Memory high byte write enable |
| MWENL | Out (CMOS) | 78 | Memory low byte write enable |
| MWRST | Out (CMOS) | 71 | Memory write reset |
| PAL | In (CMOSd) | 2 | NTSC/PAL select; 0-NTSC; 1-PAL |
| RED<7:0> | In (CMOSd) | 100-107 | Graphic red input data |
| Reset | In (62 ohm) | 42 | Full scale current adjust, 62 ohm pull-dowen |
| SCL | In (CMOSsu) | 13 | I2C clock |
| SDA | In/out (CMOSsu) | 10 | 12C data |
| SELECT | In (CMOSsd) | 5 | Select button |
| CLKTYPE | In (CMOSd) | 152 | Clock frequency; 0-28.6 Mhz for NTSC, 35.5 Mhz for PAL; 1-14.3 Mhz for NTSC, 17.7 Mhz for PAL |
| TEST1 | In (CMOSd) | 1 | Test pin |
| TEST2 | Out (CMOS) | 9 | No connect. (For chip testing) |
| TVCLK | Out (CMOS) | 151 | Clock output for graphic chip clock |
| VRB | In (0V) | 135 | Bottom voltage reference |
| VREF | In (1.23V) | 35 | Voltage reference input |
| VRT | In | 134 | Top voltage reference |
| XIN1/FIN1 | In (CMOS) | 159 | Crystal input/external clock input 1for NTSC |
| XIN2/FIN2 | In (CMOS) | 154 | Crystal input/external clock input 2 for PAL |
| XOUT1 | Out (CMOS) | 158 | Crystal output 1 for NTSC |
| XOUT2 | Out (CMOS) | 153 | Crystal output 2 for PAL |
| VDD x 13 | N/A | 8, 24, 46, 6, 1, 70, 79, 89, 99, 113, 123, 139, 144, 150 | Digital power |
| GND x 14 | N/A | 14, 19, 29, 51, 56, 67, 74, 84, 94, 108, 118, 142, 155, 160 | Digital ground |
| ADVDD x 3 | N/A | 130, 131, 138 | ADC power |
| ADGND x 3 | N/A | 128, 133, 136 | ADC ground |
| DAVDD x 3 | N/A | 35, 44, 45 | DAC power |
| DAGND x 3 | N/A | 36, 38, 40 | DAC ground |
Ordering information:
- Minimum Order: Negotiable set